The present invention generally relates to a method for manufacturing a thin-film transistor and, more particularly, to a method for the formation of a pattern of a semi-conductor layer made of tellurium (Te).
In general, a thin-film pattern formation is carried out by the employment of either a masked vapor deposition technique or a photolithographic technique. The photolithographic technique is generally recognized as a more effective and better technique than the masked vapor evaporation technique, so far as the precision of the resultant pattern and the applicability to mass production are concerned. For the purpose of the discussion of the present invention, the prior art methods for making some thin-film transistors will first be described with reference to FIGS. 1 to 4 of the accompanying drawings, all of said prior art methods utilizing the photolithographic technique.
Referring first to FIG. 1, there is shown, in a cross-sectional representation, a thin-film transistor generally referred to as a so-called "inverted-staggered type." This type of thin-film transistor is manufactured by forming a thin film of metal, such as aluminum (Al), tantalum (Ta), hafnium (Hf), titanium (Ti) or zirconium (Zr), on a substrate made of, for example, glass by the use of an electron beam deposition technique or a sputtering technique, and then forming a pattern by the use of a so-called wet-etching technique or a so-called dry-etching technique to give a gate electrode 2. The patterned gate electrode 2 so formed on the substrate 1 is then anode-oxidized to form an oxide insulating layer 3 on the gate electrode 2. The formation of the insulating layer 3 on the gate electrode 2 may be carried out by the use of the electron beam deposition technique or the sputtering technique other than the anodization technique. Thereafter, by the employment of a lift-off technique, a semiconductor layer 4 is formed on the insulating layer 3 using Te as a material. The final step is to form source and drain electrodes 5 using gold (Au) or nickel (Ni) as a material therefor, thereby completing the thin-film transistor.
Shown in FIG. 2 is a thin-film transistor of a so-called "coplanar type." This type of thin-film transistor is manufactured by forming a thin film of metal, such as Al, Ta, Hf, Ti or Zr, on a glass substrate 1 by the use of the electron beam deposition technique or the sputtering technique, followed by a pattern formation by the use of either the wet-etching technique or the dry-etching technique to form a gate electrode 2. The formation of the gate electrode 2 may be carried out by the use of the masked vacuum evaporation technique. Subsequent thereto, an oxide insulating layer 3 is formed on the gate electrode 2 by the use of the anodization technique. Either a vacuum evaporation technique or a sputtering technique may also be employable to form the insulating layer 3 in place of the anodization technique. Thereafter, a thin metal layer of Au or Ni is formed on the insulating layer 3 in any known manner, followed by the formation of source and drain electrodes 5. The final step is to form a semiconductor layer 4 of Te by the use of the lift-off technique, thereby completing the thin-film transistor of coplanar type.
A thin-film transistor of a construction shown in section in FIG. 3 is also known. This type of thin-film transistor shown in FIG. 3 is manufactured by forming a thin film of metal, such as Al, Ta, Hf, Ti or Zr, on a glass substrate 1 by the use of the electron beam deposition technique or the sputtering technique, followed by the pattern formation by the use of the dry-etching or the wet-etching technique to form a gate electrode 2. The formation of the gate electrode 2 may be carried out by the use of the masked vacuum evaporation technique. An insulating layer 3 is subsequently formed on the gate electrode by the use of either the anodization technique or one of the vacuum evaporation technique and the sputtering technique, followed by the formation of source and drain electrodes 5 by forming thin metal layer of Au or Ni in any known manner. The final step is to form a semiconductor layer 4 of Te on both of the source and drain electrodes 5 and the insulating layer 3 by the use of the lift-off technique. This semiconductor layer 4 may also be formed by the use of the masked vacuum evaporation technique.
The pattern formation of the semiconductor layer 4 according to any one of the methods shown in FIGS. 1 to 3 is carried out in a manner shown in FIG. 4.
According to the prior art, the pattern formation of the Te semiconductor layer 4 is carried out by first applying a resist material on a substrate to be patterned by the use of a spinner as shown in a step n1 in FIG. 4. The used resist material is manufactured and sold under the trade name "AZ-1350" by Shipley Company Inc. of U.S.A. and is so coated with about 0.6 .mu.m in thickness. The subsequent step n2 in FIG. 4 is to subject the substrate with the resist material applied thereon to a soft-baking process for 15 minutes at 90.degree. C., followed by exposure for 10 seconds to a 500 W-super high pressure mercury lamp at a step n3 in FIG. 4, the exposed resist on the substrate being then developed as shown in step n4 in FIG. 4. The developing of the exposed resist on the substrate is carried out for about 60 seconds at ambient (or room) temperature by the use of an aqueous solution containing an equal amount of distilled water and a developing agent manufactured and sold under the trade name "AZ Developer" by Shipley Company Inc. of U.S.A. At a step n5 in FIG. 4 followed by the step n4 in FIG. 4, the developed substrate is flushed with water and, thereafter, that is, at a step n6 in FIG. 4, the washed substrate is post-baked for 15 minutes at 110.degree. C. At a step n7 in FIG. 4 followed by the step n6 in FIG. 4, Te is vacuum-deposited on the substrate (Substrate Temperature: Ambient temperature. Pressure: 2.times.10.sup.-5 Torr. Deposition rate: 4 .ANG./sec.), followed by the final step n8 in FIG. 4 during which the Te-deposited substrate is subjected to an ultrasonic cleaning two times to remove the unwanted portion of the Te layer on the substrate, thereby completing the pattern formation.